It is known in the art for slave network nodes to perform direct clock and framing extraction on the input data stream from the master network re-create the corresponding clocking and frame reference signals on the slave network. One problem with this technique is that the clocking signals derived at the slave network tend to be subjected to jitter, as a result of having been extracted directly from the data stream, and therefore subject to the noise characteristics of the transmission line joining the master to the slave. This technique also requires that the exact framing of the master be present in some form in the data stream, usually as a start-of-frame character or signal. Also, the data stream from the master to the slave must be continuous. If there is an interruption in the data stream, the clocking and framing of the slave system is usually quite radically affected. Some systems incorporate loss-of-signal detectors and circuitry for maintaining the slave clocks approximately constant in the event of data interruption, until the data stream signal is re-established. Overall, this technique is not well suited to applications with stringent requirements on accuracy of the derived slave clock.
Phase locked loops (PLL) are well-known systems by which clocking and phasing are generated on the slave node using voltage-controlled oscillators. The initial framing of the slave is arbitrary. However, the slave node framing phase information is compared to the relative frame phasing received from the master node via the data link. An error-offset signal is calculated using the phase information from the master and the slave. The offset signal feeds back into the voltage controlled oscillator of the slave node clock generation circuits, to adjust the slave clock frequency until the master and the slave are in the desired relative phase. This frequency until the master and the slave are in the desired relative phase. This technique provides a very smooth operating slave end node that is quite resilient to transient noise characteristics on the data link. Brief interruptions in the signal are tolerated, without affecting the slave clock and framing.
The problem with prior art phase lock loops is that the circuit design is generally more complicated than direct-clock-extraction circuits. Phase lock loop circuits generally incorporate well known devices such as voltage controlled oscillators, phase comparators, etc. which cannot be easily integrated into digital CMOS ASICs. On the other hand, PLL circuits that are designed for integration into ASICs have fixed operational characteristics that are not desirable. For example, the frequency and/or phase tracking response is generally fixed. Some PLL circuits have dual or even multiple algorithms, (i.e. one for tracking the master phase and initially establishing the slave phase lock, and a different algorithm for keeping the slave circuit locked.) These circuits are usually employed because the criteria required to track the master phase and establish the slave phase under all possible conditions tend to make the slave signal unstable or jittery once the circuit is locked. Alternatively, circuits that are characterised by desirable clock quality and stability do not provide sufficient response to initially capture and lock to the master node under all conditions.
Finally, a PLL lock-holding response that provides the most desirable clock output characteristics tends to have longer time constants associated with it. Thus, for example, in the situation of a master system lock to a digital trunk (slave system), these long time constants in combination with the master tracking algorithm can cause system instability.